1. Field of the Invention
The present application relates to chip design and, in particular, to optimizing existing design rules for improving semiconductor chip fabrication yield.
2. Related Art
The fabrication of integrated circuits is an extremely complex manufacturing process that may involve hundreds of individual operations. Basically, the process includes the diffusion of precisely determined amounts of dopant material into precisely determined areas of a silicon wafer to produce active devices such as transistors. This is typically accomplished by forming a layer of silicon dioxide on the wafer, then utilizing a photo-mask and photo-resist to define a pattern of areas into which diffusion is to occur through the silicon dioxide. Openings are then etched through the silicon dioxide layer to define the pattern of precisely sized and located openings through which diffusion will take place. After a multiple such diffusion operations have been carried out to produce the desired number of transistors in the wafer, the transistors are interconnected by interconnection lines (“interconnects”). The interconnects are typically formed by deposition of an electrically conductive material, which is defined into the desired interconnect pattern by a photo-mask, photo-resist, and etching process. Typically, a completed integrated circuit has millions of transistors contained within 1 cm2 of silicon chip and interconnects of sub-micron dimensions.
In view of the device and interconnect densities and feature sizes, it is useful for designers and manufacturing engineers to work together to make changes that improve the manufacturability of a particular integrated circuit. In the past, the activity of designers and manufacturing/process engineers was kept quite isolated. Thus, if a designer obeyed a simple design rule document outlining the smallest feature size or other basic rules, the manufacturability of a particular product could be reasonably well assured.
These design rule documents are no longer sufficient. This can be explained on two main levels. First, from a random defect standpoint, the number of devices, contacts, vias, or other critical attributes on an integrated circuit has surged to approach 100 million or more. It is very difficult to reduce the failure rate of these attributes to acceptable levels to achieve desired yield targets. As such, significant yield loss occurs even for mature technologies.
Second, failure modes specific to the layout environment also occur. For example, the failure rate of contacts in a very isolated area may be very different from contacts in a very dense area because of etch loading or other pattern dependent failures. In the past, such dependencies either did not exist or were not explicitly modeled by either designers or process engineers. In both cases of either heavy use of isolated or dense contacts, the design rules are certainly followed. That is, there is no design rule limiting the number of contacts that a designer can place, nor are there explicit rules about trading off contact density versus yield. This simple example illustrates that current design rules are no longer sufficient to reasonably well assure the manufacturability of a particular product.
Thus, yield prediction and improvement methodologies have been used to better assure that a particular design will result in a manufacturable product. These methodologies are particularly important to fabless companies (i.e., companies that primarily rely on other companies or foundries for manufacturing). For these companies, improving the manufacturability of a particular integrated circuit gives a competitive advantage since the yield improvement is targeted to their products, and not for their competitors' products that may be manufactured using the same foundry. Also, the resulting yield improvement can be very rapid when control is placed with the designer.
In view of the above facts, this application considers the question of how designs are modified to improve the manufacturability of a particular integrated circuit. Such considerations have been embodied before under the rubric of design for manufacturability (DFM) or design for yield, but they have not been performed to the same level or degree of sophistication presented in this application. For example, “Yield/Reliability Enhancement Using Automated Layout Modifications”, Allan, G., ASMC 2002, pp. 252-261, Boston (USA), May 2002, which is incorporated herein by reference in its entirety, describes a method for determining layout changes purely by reducing critical area if there is enough chip area to do so. But, this determination is independent of process failure mechanisms and fail rates. The method does not include any priority in what changes will be applied and what changes could be skipped, since they are not a problem for a given process/design combination. The method also focuses on BEOL routing and does not describe a method of how to modify FEOL elements like standard cells and SRAM.
U.S. Pat. No. 6,449,749 B1, “System and Method for Product Yield Prediction,” issued Sep. 10, 2002, which is incorporated herein by reference in its entirety, describes a method of yield prediction of a product, and in particular, it teaches a method to extract the random and systematic components of the yield through the design of a test chip that reflects the existing layout properties of a product design. Although this method provides a means to estimate the manufacturability of an existing product design, it does not provide a method to interface with an existing design system and the associated IP components. This application describes a method to utilize the extracted failure rates related to a specific product design, through the use of a test chip, in order to optimize an existing or proposed design that produces an IC product with superior manufacturability attributes.